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اسلاید 1 :

Outline

  • FIR filter on ADPS-21x

DSP Requirements

  • Fast Multiply-Accumulates (Data-path)
  • Extended Precision Accumulator Register (Data-path)
  • Dual Operand Fetch (Memory)
  • Circular Buffering (Addressing)
  • Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming

  • SHARC
  • Blackfin
  • Performance Optimization

اسلاید 2 :

FIR filter steps

  1. Obtain a sample with the ADC; generate an interrupt
  2. Detect and manage the interrupt
  3. Move the sample into the input signal's circular buffer
  4. Update the pointer for the input signal's circular buffer
  5. Zero the accumulator
  6. Control the loop through each of the coefficients
  7. Fetch the coefficient from the coefficient's circular buffer
  8. Update the pointer for the coefficient's circular buffer
  9. Fetch the sample from the input signal's circular buffer
  10. Update the pointer for the input signal's circular buffer
  11. Multiply the coefficient by the sample
  12. Add the product to the accumulator
  13. Move the output sample (accumulator) to a holding buffer
  14. Move the output sample from the holding buffer to the DAC

اسلاید 3 :

FIR filter steps (cont.)

ADSP21xx Example code:

CNTR = N-1;

DO convolution UNTIL CE;

convolution:

   MR = MR + MX0 * MY0(SS), MX0 = DM(I0,M1), MY0 = PM(I4,M5);

اسلاید 4 :

  • FIR filter on ADPS-21x

DSP Requirements

  • Fast Multiply-Accumulates (Data-path)
  • Extended Precision Accumulator Register (Data-path)
  • Dual Operand Fetch (Memory)
  • Circular Buffering (Addressing)
  • Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming

  • SHARC
  • Blackfin
  • Performance Optimization

اسلاید 5 :

  • FIR filter on ADPS-21x

DSP Requirements

  • Fast Multiply-Accumulates (Data-path)
  • Extended Precision Accumulator Register (Data-path)
  • Dual Operand Fetch (Memory)
  • Circular Buffering (Addressing)
  • Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming

  • SHARC
  • Blackfin
  • Performance Optimization

اسلاید 6 :

  • FIR filter on ADPS-21x

DSP Requirements

  • Fast Multiply-Accumulates (Data-path)
  • Extended Precision Accumulator Register (Data-path)
  • Dual Operand Fetch (Memory)
  • Circular Buffering (Addressing)
  • Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming

  • SHARC
  • Blackfin
  • Performance Optimization

اسلاید 7 :

  • Software loop:

  MOVE #16,B  Initialize loop counter B

LOOP:   MAC (R0)+,(R4)+,A  Register-indirect addressing   with post-increment

  DEC B

  JNE  LOOP

  • Hardware loops: no time is spent on

–Decrementing counters

–Checking to see if the loop is finished

–Branching back to the top of the loop

 

  RPT #16

  MAC (R0)+,(R4)+,A

اسلاید 8 :

  • FIR filter on ADPS-21x

DSP Requirements

  • Fast Multiply-Accumulates (Data-path)
  • Extended Precision Accumulator Register (Data-path)
  • Dual Operand Fetch (Memory)
  • Circular Buffering (Addressing)
  • Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming

  • SHARC
  • Blackfin
  • Performance Optimization

اسلاید 9 :

  • The Super Harvard ARChitecture
  • 100MHz Core / 300 MFLOPS Peak
  • Parallel Operation of: Multiplier, ALU, 2 Address Generators &

  Sequencer

–No Arithmetic Pipeline; All Computations Are Single-Cycle

  • High Precision and Extended Dynamic Range

–32/40-Bit IEEE Floating-Point Math

–32-Bit Fixed-Point MAC’s with 64-Bit Product & 80-Bit Accumulation

  • Single-Cycle Transfers with Dual-Ported Memory Structures

–Supported by Cache Memory and Enhanced HarvardArchitecture

  • Glueless Multiprocessing Features
  • JTAG Test and Emulation Port
  • DMA Controller, Serial Ports, Link Ports, External Bus, SDRAM

  Controller, Timers

اسلاید 10 :

ADSP-2106x Core Architecture

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